MC68EC000EI8 Freescale Semiconductor, MC68EC000EI8 Datasheet - Page 36

IC MPU 32BIT 85MHZ 68-PLCC

MC68EC000EI8

Manufacturer Part Number
MC68EC000EI8
Description
IC MPU 32BIT 85MHZ 68-PLCC
Manufacturer
Freescale Semiconductor
Series
M68000r
Datasheets

Specifications of MC68EC000EI8

Processor Type
M680x0 32-Bit
Speed
8MHz
Voltage
3.3V, 5V
Mounting Type
Surface Mount
Package / Case
68-PLCC
Core Size
32 Bit
Cpu Speed
8MHz
Digital Ic Case Style
PLCC
No. Of Pins
68
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
0°C To +70°C
Filter Terminals
SMD
Rohs Compliant
Yes
Clock Frequency
8MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68EC000EI8
Manufacturer:
XILINX
Quantity:
661
Part Number:
MC68EC000EI8
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68EC000EI8R2
Quantity:
12 123
Part Number:
MC68EC000EI8R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MC68EC000EI8R2
Quantity:
63
Company:
Part Number:
MC68EC000EI8R2
Quantity:
63
Introduction
1.7 ORGANIZATION OF DATA IN REGISTERS
The following paragraphs describe data organization within the data, address, and control
registers.
1.7.1 Organization of Integer Data Formats in Registers
Each integer data register is 32 bits wide. Byte and word operands occupy the lower 8- and
16-bit portions of integer data registers, respectively. Long- word operands occupy the entire
32 bits of integer data registers. A data register that is either a source or destination operand
only uses or changes the appropriate lower 8 or 16 bits (in byte or word operations,
respectively). The remaining high-order portion does not change and goes unused. The
address of the least significant bit (LSB) of a long-word integer is zero, and the MSB is 31.
For bit fields, the address of the MSB is zero, and the LSB is the width of the register minus
one (the offset). If the width of the register plus the offset is greater than 32, the bit field
wraps around within the register. Figure 1-18 illustrates the organization of various data
formats in the data registers.
An example of a quad word is the product of a 32-bit multiply or the quotient of a 32-bit divide
operation (signed and unsigned). Quad words may be organized in any two integer data
registers without restrictions on order or pairing. There are no explicit instructions for the
management of this data format, although the MOVEM instruction can be used to move a
quad word into or out of registers.
Binary-coded decimal (BCD) data represents decimal numbers in binary form. Although
there are many BCD codes, the BCD instructions of the M68000 family support two formats,
packed and unpacked. In these formats, the LSBs consist of a binary number having the
numeric value of the corresponding decimal number. In the unpacked BCD format, a byte
defines one decimal number that has four LSBs containing the binary value and four
undefined MSBs. Each byte of the packed BCD format contains two decimal numbers; the
least significant four bits contain the least significant decimal number and the most
significant four bits contain the most significant decimal number.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
1-25

Related parts for MC68EC000EI8