MC68EC000EI8 Freescale Semiconductor, MC68EC000EI8 Datasheet - Page 525

• Manufacturer Part Number: MC68EC000EI8
• Description: IC MPU 32BIT 85MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68EC000EI8

• Processor Type: M680x0 32-Bit
• Speed: 8MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Core Size: 32 Bit
• Cpu Speed: 8MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

PTEST
Instruction Format:
Instruction Fields:
MOTOROLA
15
1
Physical Address—This 20-bit field contains the upper bits of the translated physical
R/W field—Specifies simulating a read or write bus transfer.
The MMUSR contains the results of the search. The values in the fields of the MMUSR
for a search are:
Bus Error (B)—Set if a transfer error is encountered during the table search for the
Globally Shared (G)—Set if the G-bit is set in the page descriptor.
User Page Attributes (U1, U0)—Set if corresponding bits in the page descriptor are set.
Supervisor Protection (S)—Set if the S-bit in the page descriptor is set. This bit does
Cache Mode (CM)—This 2-bit field is copied from the CM-bit in the page descriptor.
Modified (M)—Set if the M-bit is set in the page descriptor associated with the address.
Write Protect (W)—Set if the W-bit is set in any of the descriptors encountered during
Transparent Translation Register Hit (T)—Set if the PTEST address matches an
Resident (R)—Set if the PTEST address matches a transparent translation register or
Register field—Specifies the address register containing the effective address for the
0—Write
1—Read
address. Merging these bits with the lower bits of the logical address forms the
actual physical address.
14
1
PTEST instruction. If this bit is set, all other bits are zero.
not indicate that a violation has occurred.
the table search. Setting of this bit does not indicate that a violation occurred.
instruction or data transparent translation register and the R-bit is set; all other bits
are zero.
if the table search completes by obtaining a valid page descriptor.
instruction.
13
1
12
1
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
11
0
Test a Logical Address
10
1
(MC68040, MC68LC040)
9
0
8
1
7
0
6
1
R/ W
Supervisor (Privileged) Instructions
5
4
0
3
1
PTEST
2
REGISTER
1
6-71
0