MC68EC000EI8 Freescale Semiconductor, MC68EC000EI8 Datasheet - Page 545

• Manufacturer Part Number: MC68EC000EI8
• Description: IC MPU 32BIT 85MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68EC000EI8

• Processor Type: M680x0 32-Bit
• Speed: 8MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Core Size: 32 Bit
• Cpu Speed: 8MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

LPSTOP
Operation:
Assembler
Syntax:
Attributes:
Description: The immediate operand moves into the entire status register, the program
Condition Codes:
Instruction Format:
Instruction Fields:
MOTOROLA
15
1
0
Set according to the immediate operand.
Immediate field—Specifies the data to be loaded into the status register.
counter advances to point to the next instruction, and the processor stops fetching and
executing instructions. A CPU LPSTOP broadcast cycle is executed to CPU space $3
to copy the updated interrupt mask to the external bus interface (EBI). The internal
clocks are stopped.
Instruction execution resumes when a trace, interrupt, or reset exception occurs. A
trace exception will occur if the trace state is on when the LPSTOP instruction is
executed. If an interrupt request is asserted with a higher priority that the current
priority level set by the new status register value, an interrupt exception occurs;
otherwise, the interrupt request is ignored. If the bit of the immediate data
corresponding to the S-bit is off, execution of the instruction will cause a privilege
violation. An external reset always initiates reset exception processing.
14
1
0
13
1
0
12
1
0
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
If Supervisor State
Else TRAP
LPSTOP # < data >
Size = (Word) Privileged
Immediate Data
Interrupt Mask
STOP
11
1
0
10
0
0
Low-Power Stop
9
0
0
IMMEDIATE DATA
(CPU32)
External Bus Interface (EBI)
8
0
1
SR
7
0
1
6
0
1
5
0
0
4
0
0
3
0
0
LPSTOP
CPU32 Instructions
2
0
0
1
0
0
0
0
0
7-5