MC68EC000EI8 Freescale Semiconductor, MC68EC000EI8 Datasheet - Page 527

• Manufacturer Part Number: MC68EC000EI8
• Description: IC MPU 32BIT 85MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68EC000EI8

• Processor Type: M680x0 32-Bit
• Speed: 8MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Core Size: 32 Bit
• Cpu Speed: 8MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

PTEST
Operation:
Assembler
Syntax:
Attributes:
Description: If the E-bit of the translation control register is set, information about the logical
MOTOROLA
address specified by FC and < ea > is placed in the PMMU status register. If the E-bit
of the translation control register is clear, this instruction will cause a paged memory
management unit illegal operation exception (vector $39).
The function code for this operation may be specified as follows:
The effective address field specifies the logical address to be tested.
The # < level > parameter specifies the depth to which the translation table is to be
searched. A value of zero specifies a search of the address translation cache only. Val-
ues 1–7 cause the address translation cache to be ignored and specify the maximum
number of descriptors to fetch.
1. Immediate—The function code is four bits in the command word.
2. Data Register—The function code is in the lower four bits in the MC68020 data
3. Source Function Code (SFC) Register—The function code is in the SFC register
4. Destination Function Code (DFC) Register—The function code is in the DFC
register specified in the instruction.
in the CPU. Since the SFC of the MC68020 has only three implemented bits,
only function codes $0D$7 can be specified in this manner.
register in the CPU. Since the DFC of the MC68020 has only three implemented
bits, only function codes $0D$7 can be specified in this manner.
Finding an address translation cache entry with < level > set to
zero may result in a different value in the PMMU status register
than forcing a table search. Only the I, W, G, M, and C bits of the
PMMU status register are always the same in both cases.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
Get Information About Logical Address
If Supervisor State
Else TRAP
PTESTR FC, < ea > ,# < level > ,(An)
PTESTW FC, < ea > ,# < level > ,(An)
Unsized
Then Information About Logical Address
(MC68851)
NOTE
Supervisor (Privileged) Instructions
PSTATUS
PTEST
6-73