MC68EC000EI8 Freescale Semiconductor, MC68EC000EI8 Datasheet - Page 517

• Manufacturer Part Number: MC68EC000EI8
• Description: IC MPU 32BIT 85MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68EC000EI8

• Processor Type: M680x0 32-Bit
• Speed: 8MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Core Size: 32 Bit
• Cpu Speed: 8MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

PTEST
Operation:
Assembler
Syntax:
Attributes:
Description: This instruction searches the address translation cache or the translation
MOTOROLA
The < function code > operand is specified as one of the following:
tables to a specified level. Searching for the translation descriptor corresponding to the
< ea > field, it sets the bits of the MMU status register according to the status of the
descriptor. Optionally, PTEST stores the physical address of the last table entry
accessed during the search in the specified address register. The PTEST instruction
searches the address translation cache or the translation tables to obtain status
information, but alters neither the used or modified bits of the translation tables nor the
address translation cache. When the level operand is zero, only the transparent
translation of either read or write accesses causes the operations of the PTESTR and
PTESTW to return different results.
The effective address is the address to test. The < level > operand specifies the level
of the search. Level 0 specifies searching the addrass translation cache only. Levels
1–7 specify searching the translation tables only. The search ends at the specified
level. A level 0 test does not return the same MMU status register values as a test at a
nonzero level number.
Execution of the instruction continues to the requested level or until detecting one of
the following conditions:
1. Immediate—Three bits in the command word.
2. Data Register—The three least significant bits of the data register specified in
3. Source Function Code (SFC) Register
4. Destination Function Code (DFC) Register
•
•
•
the instruction.
Invalid Descriptor
Limit Violation
Bus Error Assertion (Physical Bus Error)
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
If Supervisor State
Else TRAP
PTESTR FC, < ea > ,# < level >
PTESTR FC, < ea > ,# < level > ,An
PTESTW FC, < ea > ,# < level >
PTESTW FC, < ea > ,# < level > ,An
Unsized
Then Logical Address Status
Test a Logical Address
(MC68030 only)
MMUSR
Supervisor (Privileged) Instructions
PTEST
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