UPD78F0988AGC-8BS Renesas Electronics America, UPD78F0988AGC-8BS Datasheet - Page 107

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UPD78F0988AGC-8BS

Manufacturer Part Number
UPD78F0988AGC-8BS
Description
Manufacturer
Renesas Electronics America
Datasheet

Specifications of UPD78F0988AGC-8BS

Lead Free Status / Rohs Status
Supplier Unconfirmed
5.6.2 Switching CPU clock
The following figure illustrates how the CPU clock is switched.
<1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released
<2> After the time during which the V
CPU clock
when the RESET pin is later made high, and the system clock starts oscillating. At this time, the time during
which oscillation stabilizes (2
After that, the CPU starts instruction execution at the slowest speed of the system clock (2.6 s @ 12 MHz
operation, 3.8 s @ 8.38 MHz operation).
speed has elapsed, processor clock control register (PCC) is rewritten so that the highest speed can be
selected.
RESET
V
DD1
Figure 5-5. Switching Between System Clock and CPU Clock
Internal reset operation
17
Lowest-
speed
operation
Wait (10.9 ms @ 12 MHz operation)
/f
CHAPTER 5 CLOCK GENERATOR
X
DD1
) is automatically secured.
User’s Manual U13029EJ7V1UD
voltage rises to the level at which the CPU can operate at the highest
Highest-speed
operation
105

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