UPD78F0988AGC-8BS Renesas Electronics America, UPD78F0988AGC-8BS Datasheet - Page 303

• Manufacturer Part Number: UPD78F0988AGC-8BS
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0988AGC-8BS

• Lead Free Status / Rohs Status: Supplier Unconfirmed

started from addresses written to addresses 0000H and 0001H when the RESET signal is input.
the watchdog timer. As a result, each hardware enters the status shown in Table 17-1. Each pin goes into a high-
impedance state while the RESET signal is input, and during the oscillation stabilization time immediately after the
reset function has been released.
after oscillation stabilization time (2
timer is automatically released after reset, and program execution is started after the oscillation stabilization time (2
f
X
) has elapsed (refer to Figures 17-2 to 17-4).
The reset signal can be effected by the following two methods.
(1) External reset input from RESET pin
(2) Internal reset by inadvertent program loop detection by watchdog timer
There is no functional difference between the external reset and internal reset, and execution of the program is
The reset function is effected when a low-level signal is input to the RESET pin or when an overflow occurs in
When a high-level signal is input to the RESET pin, the reset function is released, and program execution is started
Cautions 1. Input a low-level signal to the RESET pin for 10 s or longer to execute an external reset.
Count clock
2. Oscillation of the system clock is stopped while the RESET signal is being input.
3. When releasing the STOP mode by the RESET input, the contents during the STOP mode are
RESET
retained while the RESET signal is being input. However, the port pins go into a high-
impedance state.
Figure 17-1. Reset Function Block Diagram
17
/f
CHAPTER 17 RESET FUNCTION
X
) has elapsed. The reset function effected by an overflow in the watchdog
User’s Manual U13029EJ7V1UD
Watchdog timer
Stop
controller
Reset
Overflow
Reset
signal
Interrupt
function
301
17
/