UPD78F0988AGC-8BS Renesas Electronics America, UPD78F0988AGC-8BS Datasheet - Page 164

• Manufacturer Part Number: UPD78F0988AGC-8BS
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0988AGC-8BS

• Lead Free Status / Rohs Status: Supplier Unconfirmed

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10-bit compare register 3 (CM3)
CM3 is a 10-bit compare register that controls the high limit value of TM7. If the count value of TM7
matches the value of CM3 or 0, count up/down is switched at the next count clock.
CM3 provides a buffer register (BFCM3) whose contents are transferred to CM3 at the timing of interrupt
request signal INTTM7 generation.
CM3 can be written to only while TM7 is stopped.
To set the cycle to TM7, write data to BFCM3.
RESET input sets CM3 to 0FFH.
Do not set CM3 to 000H.
10-bit buffer registers 0 to 3 (BFCM0 to BFCM3)
BFCM0 to BFCM3 are 10-bit registers. They transfer data to the compare register (CM0 to CM3)
corresponding to each buffer register at the timing of interrupt request signal INTTM7 generation.
BFCM0 to BFCM3 can be read/written irrespective of whether TM7 count is stopped or operating.
RESET input sets BFCM0 to BFCM2 to 000H, and BFCM3 to 0FFH.
These registers can be read/written in word and byte units. For read/write operations of less than 8 bits,
BFCM0L to BFCM3L are used.
Dead-time reload register (DTIME)
DTIME is an 8-bit register to set dead time and is common to three dead-time timers (DTM0 to DTM2).
However, the data load timing from DTIME to DTM0, DTM1 and DTM2 is independent.
DTIME can be written only while TM7 counting is stopped. Data does not change even if an instruction
to rewrite DTIME is executed during timer operation.
RESET input sets DTIME to FFH.
Even if DTIME is set to 00H, an output with the dead time of f
Dead-time timers 0 to 2 (DTM0 to DTM2)
DTM0 to DTM2 are 8-bit down counters that generate dead time.
Count down is performed after the value of the dead-time reload register (DTIME) is reloaded with the
timing of a compare match between CM0 to CM2 and TM7. DTM0 to DTM2 generate an underflow signal
when 00H changes to FFH and stop with FFH.
The count clock is f
DTM0 to DTM2 cannot be read/written.
RESET input or clearing the CE7 bit of TMC7 sets these registers to FFH.
Buffer transfer control timer (RTM0)
RTM0 is a 3-bit up counter. It has the function of dividing interrupt request signal INTTM7.
Incrementing is performed with the TM7 underflow signal and INTTM7 is generated when the value
matches the number of divisions set with bits IDEV0 to IDEV2 of TMC7.
RTM0 cannot be read/written.
RESET input sets RTM0 to 7H. Generating INTTM7 and clearing the CE7 bit of TMC7 also sets RTM0
to 7H.
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CHAPTER 8 10-BIT INVERTER CONTROL TIMER
User’s Manual U13029EJ7V1UD
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