UPD78F0988AGC-8BS Renesas Electronics America, UPD78F0988AGC-8BS Datasheet - Page 349

• Manufacturer Part Number: UPD78F0988AGC-8BS
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0988AGC-8BS

• Lead Free Status / Rohs Status: Supplier Unconfirmed

8-bit
operation
Instruction
Group
Notes 1. When the internal high-speed RAM area is accessed or when an instruction that does not access data
Remarks 1. One clock of an instruction is equal to one CPU clock (f
2. When an area other than the internal high-speed RAM area is accessed
3. Except r = A
Mnemonic
ADDC
SUB
SUBC
2. The number of clocks shown is when the program is stored in the internal ROM area.
3. n indicates the number of wait states when the external memory expansion area is read.
is executed
register (PCC).
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
Operand
Note 3
Note 3
Note 3
CHAPTER 19 INSTRUCTION SET
User’s Manual U13029EJ7V1UD
Byte
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
Note 1 Note 2
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
Clock
9 + n
9 + n
9 + n
9 + n
9 + n
9 + n
9 + n
9 + n
9 + n
5 + n
9 + n
5 + n
9 + n
5 + n
9 + n
–
8
–
–
5
–
8
–
–
5
–
8
–
–
5
A, CY
(saddr), CY
A, CY
r, CY
A, CY
A, CY
A, CY
A, CY
A, CY
A, CY
A, CY
(saddr), CY
A, CY
r, CY
A, CY
A, CY
A, CY
A, CY
A, CY
A, CY
A, CY
(saddr), CY
A, CY
r, CY
A, CY
A, CY
A, CY
A, CY
A, CY
A, CY
CPU
r + A + CY
r – A
r – A – CY
A + (HL) + CY
A + byte + CY
A + r + CY
A + (saddr) + CY
A + (addr16) + CY
A + (HL + byte) + CY
A + (HL + B) + CY
A + (HL + C) + CY
A – byte
A – r
A – (saddr)
A – (addr16)
A – (HL)
A – (HL + byte)
A – (HL + B)
A – (HL + C)
A – byte – CY
A – r – CY
A – (saddr) – CY
A – (addr16) – CY
A – (HL) – CY
A – (HL + byte) – CY
A – (HL + B) – CY
A – (HL + C) – CY
) selected by the processor clock control
(saddr) + byte + CY
(saddr) – byte
(saddr) – byte – CY
Operation
Z AC CY
Flag
347