UPD78F0988AGC-8BS Renesas Electronics America, UPD78F0988AGC-8BS Datasheet - Page 213

• Manufacturer Part Number: UPD78F0988AGC-8BS
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0988AGC-8BS

• Lead Free Status / Rohs Status: Supplier Unconfirmed

A/D conversion
11.4.3 Operation mode of A/D converter
register 0 (ADS0).
interrupt request signal (INTAD0) is generated.
One analog input channel is selected from ANI0 to ANI7 for A/D conversion using analog input channel specification
A/D conversion can be started in the following two ways.
• Hardware start: Conversion is started by trigger input (ADTRG; rising edge/falling edge, or both rising and falling
• Software start:
The result of the A/D conversion is stored in A/D conversion result register 0 (ADCR0), and at the same time, an
(1) A/D conversion operation by hardware start
ADTRG
INTAD0
ADCR0
The A/D conversion operation is in standby when both bits 6 (TRG0) and 7 (ADCS0) of A/D converter mode
register 0 (ADM0) are set to 1. When an external trigger signal (ADTRG) is input, the voltage applied to the
analog input pin specified by analog input channel specification register 0 (ADS0) is converted into a digital value.
When A/D conversion is complete, the result of the conversion is stored in A/D conversion result register 0
(ADCR0), and an interrupt request signal (INTAD0) is generated. Once A/D conversion is started and when
one A/D conversion is complete, the next A/D conversion is not started unless a new external trigger signal
is input.
If ADS0 is rewritten during A/D conversion, the AD conversion under execution is stopped, and stands by until
a new external trigger signal is input. When the external trigger signal is input, A/D conversion is performed
again from the start. If ADS0 is rewritten while the A/D converter is standing by, the new A/D conversion
operation will be started when the next external trigger signal is input.
When 0 is written to the ADCS0 bit of ADM0 during A/D conversion, the conversion is immediately stopped.
Caution When P03/INTP3/ADTRG is used as an external trigger input (ADTRG), specify the valid edge
Remark
ADCS0 = 1, TRG0 = 1
Setting ADM0
Figure 11-6. A/D Conversion by Hardware Start (with Falling Edge Specified)
by using bits 1 and 2 (EGA00 and EGA01) of A/D converter mode register 0 (ADM0) and set
the interrupt mask flag (PMK3) to 1.
n = 0, 1, ..., 7
m = 0, 1, ..., 7
edges can be specified).
Conversion is started by setting A/D converter mode register 0 (ADM0).
Standby
status
ANIn
CHAPTER 11 A/D CONVERTER
User’s Manual U13029EJ7V1UD
ANIn
ANIn
Standby
status
ANIn
ANIn
Rewriting ADS0
Standby
status
ANIn
ANIm
ANIm
ANIm
ANIm
ANIm
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