UPD78F0988AGC-8BS Renesas Electronics America, UPD78F0988AGC-8BS Datasheet - Page 143

• Manufacturer Part Number: UPD78F0988AGC-8BS
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0988AGC-8BS

• Lead Free Status / Rohs Status: Supplier Unconfirmed

(1) 8-bit timer counters 50, 51, and 52 (TM50, TM51, and TM52)
(2) 8-bit compare registers 50, 51, and 52 (CR50, CR51, and CR52)
TM50, TM51, and TM52 are 8-bit read-only registers that count count pulses.
These counters are incremented in synchronization with the rising edge of the count clock.
TM50 and TM51, or TM51 and TM52 can be connected in cascade and used as a 16-bit timer.
When TM50 and TM51 are connected in cascade and used as a 16-bit timer, the values of these timer counters
can be read using a 16-bit manipulation instruction. TM50 and TM51 are connected with an internal 8-bit bus,
and are read one at a time. This means that the value of TM50, for example, may change while that of TM51
is read. Therefore, read TM50 and TM51 two times to compare their first and second values for the sake of
accuracy.
When TM51 and TM52 are connected in cascade and used as a 16-bit timer, they cannot be read using a
16-bit manipulation instruction. When reading TM51 and TM52, read them separately using an 8-bit
manipulation instruction.
If the count value is read during operation, input of the count clock is temporarily stopped, and the count value
at that point is read. The count value is cleared to 00H in the following cases.
<1> RESET input
<2> Clearing TCE5n
<3> Match between TM5n and CR5n in clear & start mode
Caution In a cascade connection, the 16-bit timer is cleared to 00H regardless of whether TCE51 of
Remark n = 0 to 2
The value set to CR5n is always compared with the count value of 8-bit timer counter 5n (TM5n). When the
value of the compare register matches the value of the timer counter, an interrupt request (INTTM5n) is
generated (in a mode other than the PWM mode).
The value of CR5n can be set in the range of 00H to FFH and can be rewritten during counting.
If TM50 and TM51 are connected in cascade and used as a 16-bit timer, CR50 and CR51 operate as a 16-
bit compare register. Therefore, the count value and register value are compared in 16-bit units, and if the
two values match, an interrupt request (INTTM50) is generated. At this time, the INTTM51 interrupt request
is also generated. When connecting TM50 and TM51 in cascade, therefore, mask the INTTM51 interrupt
request.
The same applies when TM51 and TM52 are connected in cascade. If the value of the 16-bit timer matches
that of the 16-bit compare register, the INTTM51 interrupt request is generated (so mask the INTTM52 interrupt
request).
CR50, CR51, and CR52 are set by an 8-bit memory manipulation instruction.
When CR50 and CR51 are connected in cascade, these registers function as the CR5 register and can be
accessed in 16 bits.
RESET input makes these registers undefined.
Caution When changing the setting value of 8-bit compare register 5n (CR5n) in cascade mode, stop
Remark n = 0 to 2
TM51 or TCE52 of TM52 is cleared.
each timer operation of 8-bit timer counter 5n (TM5n) connected in cascade.
CHAPTER 7 8-BIT TIMER/EVENT COUNTER
User’s Manual U13029EJ7V1UD
141