UPD78F0988AGC-8BS Renesas Electronics America, UPD78F0988AGC-8BS Datasheet - Page 300

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UPD78F0988AGC-8BS

Manufacturer Part Number
UPD78F0988AGC-8BS
Description
Manufacturer
Renesas Electronics America
Datasheet

Specifications of UPD78F0988AGC-8BS

Lead Free Status / Rohs Status
Supplier Unconfirmed
16.2.2 STOP mode
298
Clock generator
CPU
Output port (output latch)
16-bit timer/event counter
8-bit timer/event counter
10-bit inverter control timer
Watchdog timer
Real-time output port
A/D converter
Serial interface
External interrupt
Externally
extended
bus line
(1) Setting and operation status of STOP mode
The STOP mode is set by executing the STOP instruction.
Cautions 1. When the STOP mode is set, the X2 pin is internally pulled up to V
The following table shows the operation status in the STOP mode.
AD0 to AD7
ASTB
WR, RD
WAIT
Item
2. Because the standby mode can be released by an interrupt request signal, the standby
current leakage of the crystal oscillator block. Therefore, do not use the STOP mode in
a system where the external clock is used as the system clock.
mode is released as soon as it is set if there is an interrupt source whose interrupt request
flag is set and interrupt mask flag is reset. When the STOP mode is set, therefore, the
HALT mode is set immediately after the STOP instruction has been executed, the wait
time set by the oscillation stabilization time select register (OSTS) elapses, and then an
operation mode is set.
Table 16-3. Operation Status in STOP Mode
Oscillation stopped.
Stops operation.
Retains previous status immediately before STOP instruction execution.
Operable only when TI000 or TI001 is selected as count clock.
Operable only when TI50, TI51, or TI52 is selected as count clock.
Stops operation.
Stops operation.
Operable when external trigger is used or when TI010, TI011, or TI52 is selected as
count clock of timer/event counter.
Stops operation.
Stops operation.
Operable
High impedance
Low level
High level
High impedance
CHAPTER 16 STANDBY FUNCTION
User’s Manual U13029EJ7V1UD
Operation Status
DD1
to suppress the

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