ep1s25 Altera Corporation, ep1s25 Datasheet - Page 128

• Manufacturer Part Number: ep1s25
• Description: Stratix Device Family Data Sheet
• Manufacturer: Altera Corporation

I/O Structure
Figure 2–67. Stratix IOE in DDR Output I/O Configuration
Notes to
(1)
(2)
2–114
Stratix Device Handbook, Volume 1
Column or Row
Interconnect
All input signals to the IOE can be inverted at the IOE.
The tristate is by default active high. It can, however, be designed to be active low.
I/O Interconnect
Figure
[15..0]
IOE_CLK[7..0]
2–67:
clkout
aclr/prn
sclr
Chip-Wide Reset
Register Delay
Register Delay
Logic Array
Enable Clock
Enable Delay
Enable Delay
Logic Array
Output Clock
to Output
to Output
Output
Output Register
Output Register
OE Register
OE Register
ENA
Notes
D
CLRN/PRN
D
CLRN/PRN
D
CLRN/PRN
D
CLRN/PRN
ENA
ENA
ENA
Q
Q
Q
Q
(1),
(2)
Drive Strength Control
Used for
DDR SDRAM
Pin Delay
Output
Open-Drain Output
Slew Control
clk
t
ZX
Output
Delay
OE Register
t
CO
Delay
V
CCIO
Altera Corporation
V
CCIO
Optional
PCI Clamp
Bus-Hold
Circuit
Programmable
Pull-Up
Resistor
July 2005