ep1s25 Altera Corporation, ep1s25 Datasheet - Page 236

• Manufacturer Part Number: ep1s25
• Description: Stratix Device Family Data Sheet
• Manufacturer: Altera Corporation

Timing Model
4–66
Stratix Device Handbook, Volume 1
LVCMOS
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
1.5-V LVTTL
GTL
GTL+
3.3-V PCI
3.3-V PCI-X 1.0
Compact PCI
AGP 1×
AGP 2×
CTT
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
Table 4–103. Stratix I/O Standard Column Pin Input Delay Adders
Parameter
-5 Speed Grade
Min
External I/O Delay Parameters
External I/O delay timing parameters for I/O standard input and output
adders and programmable input and output delays are specified by
speed grade independent of device density. All of the timing parameters
in this section apply to both flip-chip and wire-bond packages.
Tables 4–103
column and row I/O pins. If an I/O standard is selected other than 3.3-V
LVTTL or LVCMOS, add the selected delay to the external t
t
INSUPLL
–162
–162
–202
–202
Max
221
352
–75
120
–76
–76
–52
–52
–45
19
78
78
I/O parameters shown in
0
0
0
0
0
0
0
and
-6 Speed Grade
Min
4–104
show the input adder delays associated with
–171
–171
–213
–213
Max
232
369
–48
–79
126
–80
–80
–55
–55
19
81
81
0
0
0
0
0
0
0
-7 Speed Grade
Min
Tables 4–54
–196
–196
–244
–244
Max
266
425
–55
–91
144
–92
–92
–63
–63
22
94
94
0
0
0
0
0
0
0
through 4–96.
-8 Speed Grade
Min
Altera Corporation
INSU
–107
–231
–231
–287
–287
–108
–108
Max
January 2006
313
500
–64
170
110
110
–74
–74
26
0
0
0
0
0
0
0
and
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps