ep1s25 Altera Corporation, ep1s25 Datasheet - Page 251

• Manufacturer Part Number: ep1s25
• Description: Stratix Device Family Data Sheet
• Manufacturer: Altera Corporation

Altera Corporation
January 2006
Tables 4–120
column and row pins in Stratix devices.
Note to
(1)
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
1.8-V HSTL Class I
CTT
Differential 1.5-V HSTL
C1
LVPECL
PCML
LVDS
HyperTransport
technology
LVTTL
2.5 V
1.8 V
1.5 V
LVCMOS
GTL
GTL+
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class I
SSTL-2 Class I
Table 4–119. Stratix Maximum Input Clock Rate for CLK[1, 3, 8, 10] Pins in
Wire-Bond Packages (Part 2 of 2)
Table 4–120. Stratix Maximum Output Clock Rate for PLL[5, 6, 11, 12] Pins
in Flip-Chip Packages (Part 1 of 2)
These parameters are only available on row I/O pins.
I/O Standard
I/O Standard
(1)
(1)
Tables 4–114
(1)
(1)
through
(3)
(4)
(5)
through 4–119:
4–123
-6 Speed
-5 Speed
Grade
Grade
350
350
350
350
250
350
645
275
645
500
350
350
250
225
350
200
200
200
200
200
200
150
show the maximum output clock rate for
-7 Speed
-6 Speed
Grade
Grade
300
300
300
300
200
300
622
275
622
450
300
300
250
200
300
167
167
167
167
200
200
134
Stratix Device Handbook, Volume 1
DC & Switching Characteristics
-8 Speed
-7 Speed
Grade
Grade
300
300
300
300
200
300
622
275
622
450
250
300
250
200
250
125
125
167
167
167
167
134
-8 Speed
Grade
250
300
250
200
250
125
125
133
133
167
167
134
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
4–81