ep1s25 Altera Corporation, ep1s25 Datasheet - Page 254

• Manufacturer Part Number: ep1s25
• Description: Stratix Device Family Data Sheet
• Manufacturer: Altera Corporation

Timing Model
4–84
Stratix Device Handbook, Volume 1
LVTTL
2.5 V
1.8 V
1.5 V
LVCMOS
GTL
GTL+
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
3.3-V PCI
3.3-V PCI-X 1.0
Compact PCI
AGP 1×
AGP 2×
CTT
Differential 1.5-V HSTL
C1
Differential 1.8-V HSTL
Class I
Differential 1.8-V HSTL
Class II
Differential SSTL-2
LVPECL
PCML
Table 4–122. Stratix Maximum Output Clock Rate for PLL[5, 6, 11, 12] Pins
in Wire-Bond Packages (Part 1 of 2)
I/O Standard
(2)
(2)
(1)
-6 Speed
Grade
175
175
175
175
175
125
125
110
133
166
133
110
110
167
167
167
167
167
167
175
175
175
125
167
167
167
110
311
250
-7 Speed
Grade
150
150
150
150
150
100
100
125
133
100
100
100
167
133
167
133
167
133
150
150
150
100
133
167
133
100
275
200
90
-8 Speed
Grade
150
150
150
150
150
100
100
125
133
100
100
100
167
133
167
133
167
150
150
150
100
133
167
133
100
275
200
133
90
Altera Corporation
January 2006
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