ep1s25 Altera Corporation, ep1s25 Datasheet - Page 203

• Manufacturer Part Number: ep1s25
• Description: Stratix Device Family Data Sheet
• Manufacturer: Altera Corporation

Altera Corporation
January 2006
External Timing Parameters
External timing parameters are specified by device density and speed
grade.
IOE pin timing. All registers are within the IOE.
Figure 4–4. External Timing in Stratix Devices
All external timing parameters reported in this section are defined with
respect to the dedicated clock pin as the starting point. All external I/O
timing parameters shown are for 3.3-V LVTTL I/O standard with the
24-mA current strength and fast slew rate. For external I/O timing using
standards other than LVTTL or for different current strengths, use the I/O
standard input and output delay adders in
Dedicated
Clock
Figure 4–4
shows the pin-to-pin timing model for bidirectional
Output Register
Input Register
OE Register
D
D
D
CLRN
CLRN
CLRN
PRN
PRN
PRN
Q
Q
Q
Stratix Device Handbook, Volume 1
DC & Switching Characteristics
Tables 4–103
Bidirectional
Pin
through 4–108.
t
t
t
t
t
INSU
INH
OUTCO
XZ
ZX
4–33