ep1s25 Altera Corporation, ep1s25 Datasheet - Page 62

• Manufacturer Part Number: ep1s25
• Description: Stratix Device Family Data Sheet
• Manufacturer: Altera Corporation

TriMatrix Memory
Figure 2–26. Input/Output Clock Mode in Simple Dual-Port Mode
Notes to
(1)
(2)
2–48
Stratix Device Handbook, Volume 1
wraddress[ ]
address[ ]
byteena[ ]
outclken
wrclock
inclken
rdclock
data[ ]
All registers shown except the rden register have asynchronous clear ports.
Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
wren
rden
Figure
8 LAB Row
Clocks
8
2–26:
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
Q
Q
Q
Q
Q
Q
Generator
Pulse
Write
Data In
Read Address
Byte Enable
Write Address
Read Enable
Write Enable
Notes
Memory Block
Data Out
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
256 ´ 16
(1),
512 ´ 8
(2)
D
ENA
Q
Altera Corporation
To MultiTrack
Interconnect
July 2005