ep1s25 Altera Corporation, ep1s25 Datasheet - Page 248

• Manufacturer Part Number: ep1s25
• Description: Stratix Device Family Data Sheet
• Manufacturer: Altera Corporation

Timing Model
4–78
Stratix Device Handbook, Volume 1
LVTTL
2.5 V
1.8 V
1.5 V
LVCMOS
GTL+
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
1.8-V HSTL Class I
CTT
Differential 1.5-V HSTL
C1
LVPECL
PCML
LVDS
HyperTransport
technology
LVTTL
2.5 V
1.8 V
1.5 V
LVCMOS
GTL
Table 4–116. Stratix Maximum Input Clock Rate for CLK[1, 3, 8, 10] Pins in
Flip-Chip Packages
Table 4–117. Stratix Maximum Input Clock Rate for CLK[7..4] & CLK[15..12]
Pins in Wire-Bond Packages (Part 1 of 2)
I/O Standard
I/O Standard
(1)
(1)
(1)
(1)
-5 Speed
-6 Speed
Grade
Grade
422
422
422
422
422
300
400
400
400
400
400
400
400
400
300
400
645
300
645
500
422
422
422
422
422
250
-6 Speed
-7 Speed
Grade
Grade
422
422
422
422
422
250
350
350
350
350
350
350
350
350
250
350
645
275
645
500
390
390
390
390
390
200
-7 Speed
-8 Speed
Grade
Grade
390
390
390
390
390
200
300
300
300
300
300
300
300
300
200
300
640
275
640
450
390
390
390
390
390
200
Altera Corporation
-8 Speed
Grade
390
390
390
390
390
200
300
300
300
300
300
300
300
300
200
300
640
275
640
450
January 2006
MHz
MHz
MHz
MHz
MHz
MHz
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit