ep1s25 Altera Corporation, ep1s25 Datasheet - Page 16

• Manufacturer Part Number: ep1s25
• Description: Stratix Device Family Data Sheet
• Manufacturer: Altera Corporation

Functional Description
Figure 2–1. Stratix Block Diagram
2–2
Stratix Device Handbook, Volume 1
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M512 RAM Blocks for
Dual-Port Memory, Shift
Registers, & FIFO Buffers
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dedicated clocks, these registers provide exceptional performance and
interface support with external memory devices such as DDR SDRAM,
FCRAM, ZBT, and QDR SRAM devices.
High-speed serial interface channels support transfers at up to 840 Mbps
using LVDS, LVPECL, 3.3-V PCML, or HyperTransport technology I/O
standards.
Figure 2–1
DSP
Block
DSP Blocks for
Multiplication and Full
Implementation of FIR Filters
shows an overview of the Stratix device.
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M4K RAM Blocks
for True Dual-Port
Memory & Other Embedded
Memory Functions
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IOEs Support DDR, PCI, GTL+, SSTL-3,
SSTL-2, HSTL, LVDS, LVPECL, PCML,
HyperTransport & other I/O Standards
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M-RAM Block
Altera Corporation
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July 2005