ep1s25 Altera Corporation, ep1s25 Datasheet - Page 268

• Manufacturer Part Number: ep1s25
• Description: Stratix Device Family Data Sheet
• Manufacturer: Altera Corporation

PLL Specifications
4–98
Stratix Device Handbook, Volume 1
t
t
f
f
t
t
t
t
t
t
t
f
EINJITTER
FCOMP
OUT
OUT_EXT
OUTDUTY
JITTER
CONFIG5,6
CONFIG11,12
SCANCLK
DLOCK
LOCK
VCO
Table 4–130. Enhanced PLL Specifications for -8 Speed Grade (Part 2 of 3)
Symbol
External feedback clock period jitter
External feedback clock
compensation time
Output frequency for internal global
or regional clock
Output frequency for external clock
(3)
Duty cycle for external clock output
(when set to 50%)
Period jitter for external clock output
(6)
Time required to reconfigure the
scan chains for PLLs 5 and 6
Time required to reconfigure the
scan chains for PLLs 11 and 12
scanclk frequency
Time required to lock dynamically
(after switchover or reconfiguring
any non-post-scale counters/delays)
(7) (11)
Time required to lock from end of
device configuration
PLL internal VCO operating range
Parameter
(4)
(5)
(11)
Min
300
0.3
0.3
(9)
45
10
Typ
±20 mUI for <200-MHz outclk
±100 ps for >200-MHz outclk
289/f
193/f
±200
600
Max
357
369
100
400
55
SCANCLK
SCANCLK
22
6
(8)
(3)
Altera Corporation
January 2006
ps or
MHz
MHz
MHz
MHz
Unit
mUI
ps
ns
μs
μs
%