ep1s25 Altera Corporation, ep1s25 Datasheet - Page 79

• Manufacturer Part Number: ep1s25
• Description: Stratix Device Family Data Sheet
• Manufacturer: Altera Corporation

Figure 2–35. Simple Multiplier Mode
Note to
(1)
Altera Corporation
July 2005
Data B
Data A
These signals are not registered or registered once to match the data path pipeline.
Figure
shiftout B
2–35:
shiftin B
shiftout A
ENA
ENA
D
D
CLRN
CLRN
DSP blocks can also implement one 36 × 36-bit multiplier in multiplier
mode. DSP blocks use four 18 × 18-bit multipliers combined with
dedicated adder and internal shift circuitry to achieve 36-bit
multiplication. The input shift register feature is not available for the
36 × 36-bit multiplier. In 36 × 36-bit mode, the device can use the register
that is normally a multiplier-result-output register as a pipeline stage for
the 36 × 36-bit multiplier.
mode.
shiftin A
signa (1)
signb (1)
Q
Q
clock
ena
aclr
ENA
D
Figure 2–36
CLRN
Q
shows the 36 × 36-bit multiply
Stratix Device Handbook, Volume 1
ENA
D
CLRN
Q
Stratix Architecture
Data Out
2–65