ep1s25 Altera Corporation, ep1s25 Datasheet - Page 249

• Manufacturer Part Number: ep1s25
• Description: Stratix Device Family Data Sheet
• Manufacturer: Altera Corporation

Altera Corporation
January 2006
GTL+
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
3.3-V PCI
3.3-V PCI-X 1.0
Compact PCI
AGP 1×
AGP 2×
CTT
Differential 1.5-V HSTL
C1
LVPECL
PCML
LVDS
HyperTransport
technology
LVTTL
2.5 V
1.8 V
1.5 V
Table 4–117. Stratix Maximum Input Clock Rate for CLK[7..4] & CLK[15..12]
Pins in Wire-Bond Packages (Part 2 of 2)
Table 4–118. Stratix Maximum Input Clock Rate for CLK[0, 2, 9, 11] Pins &
FPLL[10..7]CLK Pins in Wire-Bond Packages (Part 1 of 2)
I/O Standard
I/O Standard
(1)
(1)
(1)
(1)
-6 Speed
-6 Speed
Grade
Grade
250
300
300
300
300
300
300
300
300
300
300
422
422
422
422
422
250
300
422
215
422
422
422
422
422
422
-7 Speed
-7 Speed
Grade
Grade
200
250
250
250
250
250
250
180
180
180
180
390
390
390
390
390
180
180
400
200
400
400
390
390
390
390
Stratix Device Handbook, Volume 1
DC & Switching Characteristics
-8 Speed
-8 Speed
Grade
Grade
200
250
250
250
250
250
250
180
180
180
180
390
390
390
390
180
180
400
200
400
400
390
390
390
390
390
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
Unit
4–79