ep1s25 Altera Corporation, ep1s25 Datasheet - Page 65

• Manufacturer Part Number: ep1s25
• Description: Stratix Device Family Data Sheet
• Manufacturer: Altera Corporation

Figure 2–28. Single-Port Mode
Note to
(1)
Altera Corporation
July 2005
address[ ]
outclken
outclock
inclken
inclock
data[ ]
wren
Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
Figure
8 LAB Row
Clocks
8
2–28:
Single-Port Mode
The memory blocks also support single-port mode, used when
simultaneous reads and writes are not required. See
block in a memory block can support up to two single-port mode RAM
blocks in the M4K RAM blocks if each RAM block is less than or equal to
2K bits in size.
Note (1)
D
ENA
D
ENA
Q
Q
Generator
D
ENA
Pulse
Write
Q
Data In
Address
Write Enable
RAM/ROM
1,024 × 4
2,048 × 2
4,096 × 1
Data Out
256 × 16
512 × 8
Stratix Device Handbook, Volume 1
D
ENA
Q
Figure
Stratix Architecture
2–28. A single
To MultiTrack
Interconnect
2–51