ep1s25 Altera Corporation, ep1s25 Datasheet - Page 88

• Manufacturer Part Number: ep1s25
• Description: Stratix Device Family Data Sheet
• Manufacturer: Altera Corporation

PLLs & Clock Networks
2–74
Stratix Device Handbook, Volume 1
There are 16 dedicated clock pins (CLK[15..0]) to drive either the global
or regional clock networks. Four clock pins drive each side of the device,
as shown in
the global and regional clock networks.
Global Clock Network
These clocks drive throughout the entire device, feeding all device
quadrants. The global clock networks can be used as clock sources for all
resources within the device—IOEs, LEs, DSP blocks, and all memory
blocks. These resources can also be used for control signals, such as clock
enables and synchronous or asynchronous clears fed from the external
pin. The global clock networks can also be driven by internal logic for
internally generated global clocks and asynchronous clears, clock
enables, or other control signals with large fanout.
16 dedicated CLK pins driving global clock networks.
Figure
2–42. Enhanced and fast PLL outputs can also drive
Figure 2–42
Altera Corporation
shows the
July 2005