ep1s25 Altera Corporation, ep1s25 Datasheet - Page 246

• Manufacturer Part Number: ep1s25
• Description: Stratix Device Family Data Sheet
• Manufacturer: Altera Corporation

Timing Model
4–76
Stratix Device Handbook, Volume 1
Maximum Input & Output Clock Rates
Tables 4–114
column and row pins in Stratix devices.
LVTTL
2.5 V
1.8 V
1.5 V
LVCMOS
GTL
GTL+
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
3.3-V PCI
3.3-V PCI-X 1.0
Compact PCI
AGP 1×
AGP 2×
CTT
Differential 1.5-V HSTL
C1
LVPECL
PCML
Table 4–114. Stratix Maximum Input Clock Rate for CLK[7..4] & CLK[15..12]
Pins in Flip-Chip Packages (Part 1 of 2)
I/O Standard
(1)
(1)
through
4–119
-5 Speed
Grade
422
422
422
422
422
300
300
400
400
400
400
400
400
400
400
400
400
422
422
422
422
422
300
400
645
300
show the maximum input clock rate for
-6 Speed
Grade
422
422
422
422
422
250
250
350
350
350
350
350
350
350
350
350
350
422
422
422
422
422
250
350
645
275
-7 Speed
Grade
390
390
390
390
390
200
200
300
300
300
300
300
300
300
300
300
300
390
390
390
390
200
300
622
275
390
Altera Corporation
-8 Speed
Grade
390
390
390
390
390
200
200
300
300
300
300
300
300
300
300
300
300
390
390
390
390
390
200
300
622
275
January 2006
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit