ep1s25 Altera Corporation, ep1s25 Datasheet - Page 250

• Manufacturer Part Number: ep1s25
• Description: Stratix Device Family Data Sheet
• Manufacturer: Altera Corporation

Timing Model
4–80
Stratix Device Handbook, Volume 1
LVCMOS
GTL+
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
1.8-V HSTL Class I
CTT
Differential 1.5-V HSTL
C1
LVPECL
PCML
LVDS
HyperTransport
technology
LVTTL
2.5 V
1.8 V
1.5 V
LVCMOS
GTL+
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
Table 4–118. Stratix Maximum Input Clock Rate for CLK[0, 2, 9, 11] Pins &
FPLL[10..7]CLK Pins in Wire-Bond Packages (Part 2 of 2)
Table 4–119. Stratix Maximum Input Clock Rate for CLK[1, 3, 8, 10] Pins in
Wire-Bond Packages (Part 1 of 2)
I/O Standard
I/O Standard
(1)
(1)
(1)
(1)
-6 Speed
-6 Speed
Grade
Grade
422
250
350
350
350
350
350
350
350
350
250
350
717
375
717
717
422
422
422
422
422
250
350
350
350
350
-7 Speed
-7 Speed
Grade
Grade
390
200
300
300
300
300
300
300
300
300
200
300
640
350
640
640
390
390
390
390
390
200
300
300
300
300
-8 Speed
-8 Speed
Grade
Grade
390
200
300
300
300
300
300
300
300
300
200
300
640
350
640
640
390
390
390
390
390
200
300
300
300
300
Altera Corporation
January 2006
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
Unit