ep1s25 Altera Corporation, ep1s25 Datasheet - Page 204

• Manufacturer Part Number: ep1s25
• Description: Stratix Device Family Data Sheet
• Manufacturer: Altera Corporation

Timing Model
4–34
Stratix Device Handbook, Volume 1
Table 4–52
regional clock networks.
Table 4–53
regional clock networks.
Notes to
(1)
(2)
t
t
t
t
t
t
t
t
t
t
t
INSU
INH
OUTCO
XZ
ZX
INSU
INH
OUTCO
INSUPLL
INHPLL
OUTCOPLL
Table 4–52. Stratix Fast Regional Clock External I/O Timing Parameters
Table 4–53. Stratix Regional Clock External I/O Timing Parameters (Part 1
of 2)
Symbol
Symbol
Notes
These timing parameters are sample-tested only.
These timing parameters are for column and row IOE pins. You should use the
Quartus II software to verify the external timing for any pin.
Notes
(1),
Table
shows the external I/O timing parameters when using fast
shows the external I/O timing parameters when using
Setup time for input or bidirectional pin using IOE input register with
fast regional clock fed by
Hold time for input or bidirectional pin using IOE input register with
fast regional clock fed by
Clock-to-output delay output or bidirectional pin using IOE output
register with fast regional clock fed by
Synchronous IOE output enable register to output pin disable delay
using fast regional clock fed by
Synchronous IOE output enable register to output pin enable delay
using fast regional clock fed by
(2)
Setup time for input or bidirectional pin using IOE input register with
regional clock fed by
Hold time for input or bidirectional pin using IOE input register with
regional clock fed by
Clock-to-output delay output or bidirectional pin using IOE output
register with regional clock fed by
Setup time for input or bidirectional pin using IOE input register with
regional clock fed by Enhanced PLL with default phase setting
Hold time for input or bidirectional pin using IOE input register with
regional clock fed by Enhanced PLL with default phase setting
Clock-to-output delay output or bidirectional pin using IOE output
register with regional clock Enhanced PLL with default phase setting
(1),
4–52:
(2)
CLK
CLK
FCLK
FCLK
pin
pin
Parameter
Parameter
FCLK
pin
pin
FCLK
CLK
FCLK
pin
pin
pin
pin
Altera Corporation
January 2006