ep1s25 Altera Corporation, ep1s25 Datasheet - Page 142

• Manufacturer Part Number: ep1s25
• Description: Stratix Device Family Data Sheet
• Manufacturer: Altera Corporation

I/O Structure
2–128
Stratix Device Handbook, Volume 1
Notes to
(1)
(2)
Differential termination (1),
Table 2–33. Differential Termination Supported by I/O Banks
Differential Termination Support
Clock pin CLK0, CLK2, CLK9, CLK11, and pins FPLL[7..10]CLK do not support differential termination.
Differential termination is only supported for LVDS because of a 3.3-V V
Table
2–33:
(2)
Figure 2–71. LVDS Input Differential On-Chip Termination
I/O banks on the left and right side of the device support LVDS receiver
(far-end) differential termination.
Table 2–33
Table 2–34
The differential on-chip resistance at the receiver input buffer is
118
Top and bottom I/O banks (3, 4, 7, and 8)
DIFFIO_RX[]
CLK[0,2,9,11],CLK[4-7],CLK[12-15]
CLK[1,3,8,10]
FCLK
FPLL[7..10]CLK
Table 2–34. Differential Termination Support Across Pin Types
Ω ±
20 %.
I/O Standard Support
Transmitting
shows the Stratix device differential termination support.
shows the termination support for different pin types.
Device
+
Ð
LVDS
Pin Type
Banks (3, 4, 7 & 8)
Z
Z
Top & Bottom
0
0
C C I O
.
Differential Termination
Receiving Device with
R
D
Left & Right Banks
Altera Corporation
(1, 2, 5 & 6)
+
Ð
v
R
v
v
July 2005
D