h8s-2161b Renesas Electronics Corporation., h8s-2161b Datasheet - Page 14

• Manufacturer Part Number: h8s-2161b
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Rev. 3.00 Mar 21, 2006 page xiv of liv
Item
16.4.4 Master
Receive Operation
Figure 16.15 Sample
Flowchart for
Operations in Master
Receive (Receiving a
Single Byte) (WAIT =
1)
Figure 16.16 Example
of Master Receive
Mode Operation
Timing (MLS = ACKB
= 0, WAIT = 1)
16.4.5 Slave Receive
Operation
Figure 16.22 Example
of Slave Receive Mode
Operation Timing (1)
(MLS = ACKB = 0,
HNDS = 0)
Figure 16.23 Example
of Slave Receive Mode
Operation Timing (2)
(MLS = ACKB = 0,
HNDS = 0)
16.6 Usage Notes
Figure 16.35 ICDR
Read and ICCR
Access Riming in
Slave Transmit Mode
Page
453
456
464
464
483
485
487,
488
Revision (See Manual for Details)
Figure 16.15 amended
Figure 16.16 amended
(master output)
(master output)
Figure title amended
Figure title amended
10. Notes on WAIT Function
Description added
Figure 16.35 amended
R/W
14. Notes on Arbitration Lost in Master Mode
Description added
(slave output)
SDA
SCL
SDA
Master tansmit mode
IRIC
No
Read IRIC flag in ICCR
Set ACKB = 1 in ICSR
9
A
Read ICDR
IRIC = 1?
Master receive mode
Yes
Bit 7
1
Bit 6
2
Bit 5
3
Data 1
Bit 4
4
Bit 3
[2] Start receiving. The first read
[3] Wait for a receive wait
[7] Set acknowledge data for
5
Bit 2
is a dummy read.
(Set IRIC at the fall of the 8th clock)
the last reception.
6
Bit 1
7
Bit 0
8
[3]
A
9
[3]
Bit 7
1
Bit 6
2
Data 2
Bit 5
3
Bit 4
4
Bit 3
5