h8s-2161b Renesas Electronics Corporation., h8s-2161b Datasheet - Page 539

• Manufacturer Part Number: h8s-2161b
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

12. Note on ICDR read and ICCR access in slave transmit mode
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 1 in
In I
during the time shaded in figure 16.35. However, such read and write operations cause no
problem in interrupt handling processing that is generated in synchronization with the rising
edge of the 9th clock pulse because the shaded time has passed before making the transition to
interrupt handling.
To handle interrupts securely, be sure to keep either of the following conditions.
2
Read ICDR data that has been received so far or read/write from/to ICCR before starting
the receive operation of the next slave address.
Monitor the BC2 to BC0 bit counter in ICMR; when the count is 000 (8th or 9th clock
pulse), wait for at least two transfer clock times in order to read ICDR or read/write from/to
ICCR during the time other than the shaded time.
C bus interface slave transmit mode, do not read ICDR or do not read/write from/to ICCR
ICXR.
Figure 16.35 ICDR Read and ICCR Access Timing in Slave Transmit Mode
TRS bit
SDA
SCL
Address reception
R/W
8
The rise of the 9th clock is detected
Waveform at problem occurrence
A
9
ICDR read and ICCR read/write are disabled
(6 system clock period)
Section 16 I
Rev. 3.00 Mar 21, 2006 page 485 of 788
2
C Bus Interface (IIC) (Optional)
ICDR write
Data transmission
Bit 7
REJ09B0300-0300