h8s-2161b Renesas Electronics Corporation., h8s-2161b Datasheet - Page 399
h8s-2161b
Manufacturer Part Number
h8s-2161b
Description
Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.H8S-2161B.pdf
(845 pages)
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This LSI incorporates two watchdog timer channels (WDT_0 and WDT_1). The watchdog timer
can generate an internal reset signal or an internal NMI interrupt signal if a system crash prevents
the CPU from writing to the timer counter, thus allowing it to overflow. Simultaneously, it can
output an overflow signal (RESO) externally.
When this watchdog function is not needed, the WDT can be used as an interval timer. In interval
timer operation, an interval timer interrupt is generated each time the counter overflows. A block
diagram of the WDT_0 and WDT_1 is shown in figure 14.1.
14.1
Watchdog Timer Mode:
Internal Timer Mode:
WDT0102A_010020020700
Selectable from eight (WDT_0) or 16 (WDT_1) counter input clocks.
Switchable between watchdog timer mode and interval timer mode
If the counter overflows, an internal reset or an internal NMI interrupt is generated.
When the LSI is selected to be internally reset at counter overflow, a low level signal is output
from the RESO pin if the counter overflows.
If the counter overflows, an internal timer interrupt (WOVI) is generated.
Features
Section 14 Watchdog Timer (WDT)
Rev. 3.00 Mar 21, 2006 page 345 of 788
Section 14 Watchdog Timer (WDT)
REJ09B0300-0300
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