h8s-2161b Renesas Electronics Corporation., h8s-2161b Datasheet - Page 161

• Manufacturer Part Number: h8s-2161b
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

5.6.2
In interrupt control mode 1, mask control is applied to three levels for IRQ and on-chip peripheral
module interrupt requests by comparing the I and UI bits in CCR in the CPU, and the ICR setting.
For instance, the state transition when the interrupt enable bit corresponding to each interrupt is set
to 1, and ICRA to ICRC are set to H'20, H'00, and H'00, respectively (IRQ2 and IRQ3 interrupts
are set to control level 1, and other interrupts are set to control level 0) is shown below. Figure 5.5
shows a state transition diagram.
An interrupt request with interrupt control level 0 is accepted when the I bit in CCR is cleared
to 0. When the I bit is set to 1, the interrupt request is held pending
An interrupt request with interrupt control level 1 is accepted when the I bit or UI bit in CCR is
cleared to 0. When both I and UI bits are set to 1, the interrupt request is held pending.
All interrupt requests are accepted when I = 0. (Priority order: NMI > IRQ2 > IRQ3 > address
break > IRQ0 > IRQ1 …)
Only NMI, IRQ2, IRQ3 and address break interrupt requests are accepted when I = 1 and UI =
0.
Only an NMI and address break interrupt request is accepted when I = 1 and UI = 1.
Exception handling execution
Interrupt Control Mode 1
All interrupt requests
or I
are accepted
Figure 5.5 State Transition in Interrupt Control Mode 1
1, UI
1
I
interrupt requests are accepted
Only NMI and address break
0
I
1, UI
I
0
0
UI
Rev. 3.00 Mar 21, 2006 page 107 of 788
0
Only NMI, address break, IRQ2,
Exception handling
execution or UI
and IRQ3 interrupt requests
Section 5 Interrupt Controller
are accepted
1
REJ09B0300-0300