h8s-2161b Renesas Electronics Corporation., h8s-2161b Datasheet - Page 597

• Manufacturer Part Number: h8s-2161b
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

19.3.3
LADR3 comprises two 8-bit readable/writable registers that perform LPC channel-3 host address
setting and control the operation of the bidirectional data registers. The contents of the address
field in LADR3 must not be changed while channel 3 is operating (while LPC3E is set to 1).
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
LADR3H
LADR3L
Bit Name Initial Value R/W
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit Name Initial Value R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 1
TWRE
LPC Channel 3 Address Register (LADR3)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Channel 3 Address Bits 15 to 8:
When LPC3E = 1, an I/O address received in an LPC I/O
cycle is compared with the contents of LADR3. When
determining an IDR3, ODR3, or STR3 address match, bit 0
of LADR3 is regarded as 0, and the value of bit 2 is ignored.
When determining a TWR0 to TWR15 address match, bit 4
of LADR3 is inverted, and the values of bits 3 to 0 are
ignored. Register selection according to the bits ignored in
address match determination is as shown in table 19.2.
Description
Channel 3 Address Bits 7 to 3
Reserved
This bit is readable/writable, however, only 0 should be
written to this bit.
Channel 3 Address Bit 1
Bidirectional Data Register Enable
Enables or disables bidirectional data register operation.
0: TWR operation is disabled
TWR-related I/O address match determination is halted
1: TWR operation is enabled
Section 19 Host Interface LPC Interface (LPC)
Rev. 3.00 Mar 21, 2006 page 543 of 788
REJ09B0300-0300