h8s-2161b Renesas Electronics Corporation., h8s-2161b Datasheet - Page 173

• Manufacturer Part Number: h8s-2161b
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

5.8.2
The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these
instructions are executed, all interrupts including NMI are disabled and the next instruction is
always executed. When the I bit or UI bit is set by one of these instructions, the new value
becomes valid two states after execution of the instruction ends.
5.8.3
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer
is not accepted until the move is completed.
With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction. Therefore, if an interrupt is generated during execution
of an EEPMOV.W instruction, the following coding should be used.
5.8.4
When a product, in which a DTC is incorporated, is used in the following settings, the
corresponding flag bit is not automatically cleared even when exception handing, which is a clear
condition, is executed and the bit is held at 1.
1. When DTCEA3 is set to 1(ADI is set to an interrupt source), IRQ4F flag is not automatically
2. When DTCEA2 is set to 1(ICIA is set to an interrupt source), IRQ5F flag is not automatically
3. When DTCEA1 is set to 1(ICIB is set to an interrupt source), IRQ6F flag is not automatically
4. When DTCEA0 is set to 1(OCIA is set to an interrupt source), IRQ7F flag is not automatically
When activation interrupt sources of DTC and IRQ interrupts are used with the above
combinations, clear the interrupt flag by software in the interrupt handling routine of the
corresponding IRQ.
L1:
cleared.
cleared.
cleared.
cleared.
Instructions that Disable Interrupts
Interrupts during Execution of EEPMOV Instruction
Setting on Product Incorporating DTC
EEPMOV.W
MOV.W
BNE
R4,R4
L1
Rev. 3.00 Mar 21, 2006 page 119 of 788
Section 5 Interrupt Controller
REJ09B0300-0300