h8s-2161b Renesas Electronics Corporation., h8s-2161b Datasheet - Page 170

• Manufacturer Part Number: h8s-2161b
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 5 Interrupt Controller
5.7.3
If the CPU prefetches an address specified in BAR by setting ABRKCR and BAR, an address
break interrupt can be generated. This address break function generates an interrupt request to the
interrupt controller at prefetch, and determines the priority by the interrupt controller. When an
interrupt is accepted, an interrupt exception handling is activated after the current instruction has
been completed. Note that the interrupt mask control according to the I and UI bits in CCR of the
CPU is invalid to an address break interrupt.
To use the address break function, set each register as follows:
1. Set a break address in the A23 to A1 bits in BAR.
2. Set the BIE bit in ABRKCR to 1 to enable the address break.
When the setting conditions are satisfied, the CMF flag in ABRKCR is set to 1 to request an
interrupt. The interrupt source should be determined by the interrupt handling routine if necessary.
5.7.4
1. In an address break, the break address should be an address where the first byte of the
2. In normal mode, addresses A23 to A16 are not compared.
3. When the branch instructions (Bcc, BSR), jump instructions (JMP, JSR), RST instruction, and
4. An address break interrupt is generated by combining the internal prefetch signal and an
Figure 5.10 shows an example of address timing.
Rev. 3.00 Mar 21, 2006 page 116 of 788
REJ09B0300-0300
When the BIE bit is cleared to 0, an address break is not requested.
instruction exists. Otherwise, a break condition will not be satisfied.
RTE instruction are placed immediately prior to the address specified by BAR, a prefetch
signal to the address may be output to request an address break by executing these instruction.
It is necessary to take countermeasures: do not set a break address to an address immediately
after these instructions, or determine whether interrupt handling is performed by satisfaction of
a normal condition.
address. Therefore, the timing to enter the interrupt exception handling differs according to the
instructions at the specified and at prior addresses and execution cycles.
Operation
Usage Notes