h8s-2161b Renesas Electronics Corporation., h8s-2161b Datasheet - Page 502

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h8s-2161b

Manufacturer Part Number
h8s-2161b
Description
Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
Section 16 I
16.4.4
In I
and returns an acknowledge signal. The slave device transmits data.
The master device transmits data containing the slave address and R/W (1: read) in the first frame
following the start condition issuance in master transmit mode, selects the slave device, and then
switches the mode for receive operation.
Rev. 3.00 Mar 21, 2006 page 448 of 788
REJ09B0300-0300
(slave output)
(master output)
(master output)
User processing
2
C bus format master receive mode, the master device outputs the receive clock, receives data,
ICDRE
SDA
ICDR
IRTR
IRIC
SDA
SCL
Master Receive Operation
Data 1
Figure 16.10 Example of Stop Condition Issuance Operation Timing
2
Bit 0
C Bus Interface (IIC) (Optional)
8
Data 1
[9] ICDR write
[7]
A
9
in Master Transmit Mode (MLS = WAIT = 0)
Bit 7
1
Bit 6
[9] IRIC clear
2
Bit 5
3
Bit 4
4
Data 2
Bit 3
5
Bit 2
6
Data 2
Bit 1
7
[11] ACKB read
Bit 0
8
[12] IRIC clear
[10]
A
9
Start condition issuance
[12] Set BBSY=1and
(Stop condition issuance)
SCP=0

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