h8s-2161b Renesas Electronics Corporation., h8s-2161b Datasheet - Page 392

• Manufacturer Part Number: h8s-2161b
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 13 Timer Connection
13.4.6
Internal Synchronization Signal Generation (IHG/IVG/CL4 Signal Generation)
By using the timer connection facility, FRT, and TMR_Y, it is possible to automatically generate
internal signals (IHG and IVG signals) corresponding to the IHI and IVI signals. As the IHG
signal is synchronized with the rise of the IVG signal, the IHG signal period must be made a
divisor of the IVG signal period in order to keep it constant. In addition, the CL4 signal can be
generated in synchronization with the IHG signal.
The contents of OCRA in the FRT are updated by the automatic addition of the contents of
OCRAR or OCRAF, alternately, each time a compare-match occurs. A value corresponding to the
0 interval of the IVG signal is written in OCRAR, and a value corresponding to the 1 interval of
the IVG signal is written in OCRAF. The IVG signal is set by a compare-match after an OCRAR
addition, and reset by a compare-match after an OCRAF addition.
The IHG signal is the TMR_Y timer output. TMR_Y is set to count internal clock pulses, and to
be cleared on a TCORA compare-match, to fix the period and set the timer output. TCORB is set
so as to reset the timer output. The IVG signal is connected as the TMR_Y reset input (TMRI),
and the rise of the IVG signal can be treated in the same way as a TCORA compare-match.
The CL4 signal is a waveform that rises within one system clock period after the fall of the IHG
signal, and has an interval of 1 for 6 system clock periods.
Examples of TCR, TCSR, TCORA, and TCORB settings in TMR_Y, and TCR, OCRAR,
OCRAF, and TOCR settings in the FRT are shown in table 13.9, and the IHG signal/IVG signal
timing chart is shown in figure 13.8.
Rev. 3.00 Mar 21, 2006 page 338 of 788
REJ09B0300-0300