h8s-2161b Renesas Electronics Corporation., h8s-2161b Datasheet - Page 540

• Manufacturer Part Number: h8s-2161b
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 16 I
13. Note on TRS bit setting in slave mode
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 1 in
Rev. 3.00 Mar 21, 2006 page 486 of 788
REJ09B0300-0300
In I
edge of the 9th clock pulse or the stop condition before detecting the next rising edge on the
SCL pin (the time indicated as (a) in figure 16.36), the bit value becomes valid immediately
when it is set. However, if the TRS bit is set during the other time (the time indicated as (b) in
figure 16.36), the bit value is suspended and remains invalid until the rising edge of the 9th
clock pulse or the stop condition is detected. Therefore, when the address is received after the
restart condition is input without the stop condition, the effective TRS bit value remains 1
(transmit mode) internally and thus the acknowledge bit is not transmitted after the address has
been received at the 9th clock pulse.
To receive the address in slave mode, clear the TRS bit to 0 during the time indicated as (a) in
figure 16.36. To release the SCL low level that is held by means of the wait function in slave
mode, clear the TRS bit to and then dummy-read ICDR.
SDA
TRS
SCL
2
C bus interface slave mode, if the TRS bit value in ICCR is set after detecting the rising
ICXR.
transmission
2
C Bus Interface (IIC) (Optional)
Data
The rise of the 9th clock is detected
8
9
TRS bit setting
(a)
Figure 16.36 TRS Bit Set Timing in Slave Mode
ICDR dummy read
Restart condition
TRS bit setting is suspended in this period
1
Address reception
2
(b)
3
4
5
6
7
The rise of the 9th clock is detected
8
9
A