h8s-2161b Renesas Electronics Corporation., h8s-2161b Datasheet - Page 43

• Manufacturer Part Number: h8s-2161b
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Figure 15.27 Sample Flowchart for Mode Transition during Reception................................... 410
Figure 15.28 Switching from SCK Pins to Port Pins ................................................................ 411
Figure 15.29 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins ........ 411
Section 16 I
Figure 16.1
Figure 16.2
Figure 16.3
Figure 16.4
Figure 16.5
Figure 16.6
Figure 16.7
Figure 16.8
Figure 16.9
Figure 16.10 Example of Stop Condition Issuance Operation Timing in Master Transmit
Figure 16.11 Sample Flowchart for Operations in Master Receive Mode (HNDS = 1) ........... 449
Figure 16.12 Example of Operation Timing in Master Receive Mode
Figure 16.13 Example of Stop Condition Issuance Operation Timing in Master Receive
Figure 16.14 Sample Flowchart for Operations in Master Receive Mode
Figure 16.15 Sample Flowchart for Operations in Master Receive Mode
Figure 16.16 Example of Master Receive Mode Operation Timing
Figure 16.17 Example of Stop Condition Issuance Timing in Master Receive Mode
Figure 16.18 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 1).............. 458
Figure 16.19 Example of Slave Receive Mode Operation Timing (1) (MLS = 0, HNDS= 1).. 460
Figure 16.20 Example of Slave Receive Mode Operation Timing (2) (MLS = 0, HNDS= 1).. 461
Figure 16.21 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0).............. 462
Figure 16.22 Example of Slave Receive Mode Operation Timing (1)
Figure 16.23 Example of Slave Receive Mode Operation Timing (2)
Figure 16.24 Sample Flowchart for Slave Transmit Mode ....................................................... 465
Figure 16.25 Example of Slave Transmit Mode Operation Timing (MLS = 0) ........................ 467
Figure 16.26 IRIC Setting Timing and SCL Control (1)........................................................... 468
Figure 16.27 IRIC Setting Timing and SCL Control (2)........................................................... 469
2
C Bus Interface (IIC) (Optional)
Block Diagram of I
I
I
I
I
I
Sample Flowchart for IIC Initialization ............................................................... 444
Sample Flowchart for Operations in Master Transmit Mode............................... 445
Example of Operation Timing in Master Transmit Mode (MLS = WAIT = 0) ... 447
Mode (MLS = WAIT = 0) ................................................................................... 448
(MLS = WAIT = 0, HNDS = 1)........................................................................... 451
Mode (MLS = WAIT = 0, HNDS = 1) ................................................................ 451
(Receiving Multiple Bytes) (WAIT = 1).............................................................. 452
(Receiving a Single Byte) (WAIT = 1) ................................................................ 453
(MLS = ACKB = 0, WAIT = 1) .......................................................................... 456
(MLS = ACKB = 0, WAIT = 1) .......................................................................... 456
(MLS = ACKB = 0, HNDS = 0) .......................................................................... 464
(MLS = ACKB = 0, HNDS = 0) .......................................................................... 464
2
2
2
2
2
C Bus Interface Connections (Example: This LSI as Master) ........................... 416
C Bus Data Format (I
C Bus Data Format (Formatless) (IIC_0 Only) ................................................. 442
C Bus Data Format (Serial Format)................................................................... 443
C Bus Timing .................................................................................................... 443
2
C Bus Interface .................................................................... 415
2
C Bus Format) ................................................................ 442
Rev. 3.00 Mar 21, 2006 page xliii of liv