h8s-2161b Renesas Electronics Corporation., h8s-2161b Datasheet - Page 527

• Manufacturer Part Number: h8s-2161b
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

16.4.11 Initialization of Internal State
The IIC has a function for forcible initialization of its internal state if a deadlock occurs during
communication.
Initialization is executed in accordance with the setting of bits CLR3 to CLR0 in DDCSWR or
clearing ICE bit. For details on the setting of bits CLR3 to CLR0, see section 16.3.7, DDC Switch
Register (DDCSWR).
Scope of Initialization: The initialization executed by this function covers the following items:
The following items are not initialized:
ICDRE and ICDRF internal flags
Transmit/receive sequencer and internal operating clock counter
Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data
output, etc.)
Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, ICXR (except for the ICDRE
and ICDRF flags), DDCSWR)
Internal latches used to retain register read information for setting/clearing flags in ICMR,
ICCR, ICSR, and DDCSWR
The value of the ICMR bit counter (BC2 to BC0)
Generated interrupt sources (interrupt sources transferred to the interrupt controller)
SCL or
SDA input
signal
Sampling
clock
D
Figure 16.29 Block Diagram of Noise Canceler
Sampling clock
System clock
cycle
Latch
C
Q
D
Latch
C
Section 16 I
Q
Rev. 3.00 Mar 21, 2006 page 473 of 788
detector
2
C Bus Interface (IIC) (Optional)
Match
REJ09B0300-0300
Internal
SCL or
SDA
signal