PIC18F24J11 MICROCHIP [Microchip Technology], PIC18F24J11 Datasheet - Page 178
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PIC18F24J11
Manufacturer Part Number
PIC18F24J11
Description
28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F24J11.pdf
(536 pages)
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PIC18F46J11 FAMILY
11.1.2
The PMP module uses eight registers for transferring
data into and out of the microcontroller. They are
arranged as four pairs to allow the option of 16-bit data
operations:
• PMDIN1H and PMDIN1L
• PMDIN2H and PMDIN2L
• PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L
• PMDOUT2H and PMDOUT2L
The PMDIN1 register is used for incoming data in Slave
modes and both input and output data in Master
modes. The PMDIN2 register is used for buffering input
data in select Slave modes.
The PMADDR/PMDOUT1 registers are actually a
single register pair; the name and function are dictated
by the module’s operating mode. In Master modes, the
registers function as the PMADDRH and PMADDRL
registers and contain the address of any incoming or
outgoing data. In Slave modes, the registers function
as PMDOUT1H and PMDOUT1L and are used for
outgoing data.
DS39932D-page 178
DATA REGISTERS
PMADDRH differs from PMADDRL in that it can also
have limited PMP control functions. When the module is
operating in select Master mode configurations, the
upper two bits of the register can be used to determine
the operation of chip select signals. If these are not
used, PMADDR simply functions to hold the upper 8 bits
of the address.
the individual bits in PMADDRH.
The PMDOUT2H and PMDOUT2L registers are only
used in Buffered Slave modes and serve as a buffer for
outgoing data.
11.1.3
In addition to the module level configuration options,
the PMP module can also be configured at the I/O pin
for electrical operation. This option allows users to
select either the normal Schmitt Trigger input buffer on
digital I/O pins shared with the PMP, or use TTL level
compatible buffers instead. Buffer configuration is
controlled by the PMPTTL bit in the PADCFG1 register.
PAD CONFIGURATION CONTROL
REGISTER
Register 11-9
2011 Microchip Technology Inc.
provides the function of
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