PIC18F24J11 MICROCHIP [Microchip Technology], PIC18F24J11 Datasheet - Page 266

• Manufacturer Part Number: PIC18F24J11
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F46J11 FAMILY
REGISTER 18-3:
18.5.7
In Single Output mode, pulse steering allows any of the
PWM pins to be the modulated signal. Additionally, the
same PWM signal can simultaneously be available on
multiple pins.
Once
(CCPxM<3:2> = 11 and PxM<1:0> = 00 of the
CCPxCON register), the user firmware can bring out
the same PWM signal to one, two, three or four output
pins by setting the appropriate STR<D:A> bits of the
PSTRxCON register, as provided in
DS39932D-page 266
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-0
Note:
PxRSEN
R/W-0
the
PULSE STEERING MODE
The associated TRIS bits must be set to
output (‘0’) to enable the pin output driver
in order to see the PWM signal on the pin.
Single
PxRSEN: PWM Restart Enable bit
1 = Upon auto-shutdown, the ECCPxASE bit clears automatically once the shutdown event goes
0 = Upon auto-shutdown, ECCPxASE must be cleared by software to restart the PWM
PxDC<6:0>: PWM Delay Count bits
PxDCn = Number of F
PxDC6
R/W-0
away; the PWM restarts automatically
ECCPxDEL: ENHANCED PWM CONTROL REGISTER (ACCESS FBDh/FB7h)
Output
should transition active and the actual time it transitions active.
W = Writable bit
‘1’ = Bit is set
mode
PxDC5
R/W-0
Table
OSC
is
18-4.
/4 (4 * T
selected
PxDC4
R/W-0
OSC
) cycles between the scheduled time when a PWM signal
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PxDC3
R/W-0
While the PWM Steering mode is active, the
CCPxM<1:0> bits of the CCPxCON register select the
PWM output polarity for the Px<D:A> pins.
The PWM auto-shutdown operation also applies to
PWM Steering mode as described in Section 18.5.4
“Enhanced
auto-shutdown event will only affect pins that have
PWM outputs enabled.
PxDC2
R/W-0
PWM
Auto-shutdown
 2011 Microchip Technology Inc.
x = Bit is unknown
PxDC1
R/W-0
mode”.
PxDC0
R/W-0
bit 0
An