PIC18F24J11 MICROCHIP [Microchip Technology], PIC18F24J11 Datasheet - Page 276

• Manufacturer Part Number: PIC18F24J11
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F46J11 FAMILY
19.3.4
To enable the serial port, MSSP Enable bit, SSPEN
(SSPxCON1<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, reinitialize the
SSPxCON1 registers and then set the SSPEN bit. This
configures the SDIx, SDOx, SCKx and SSx pins as
serial port pins. For the pins to behave as the serial port
function, the appropriate TRIS bits, ANCON/PCFG bits
and Peripheral Pin Select registers (if using MSSP2)
should be correctly initialized prior to setting the
SSPEN bit.
A typical SPI serial port initialization process follows:
• Initialize ODCON3 register (optional open-drain
• Initialize remappable pin functions (if using
• Initialize SCKx LAT value to desired Idle SCK
• Initialize SCKx ANCON/PCFG bit (if Slave mode
• Initialize SCKx TRIS bit as output (Master mode)
• Initialize SDIx ANCON/PCFG bit (if SDIx is
• Initialize SDIx TRIS bit
• Initialize SSx ANCON/PCFG bit (if Slave mode
• Initialize SSx TRIS bit (Slave modes)
• Initialize SDOx TRIS bit
• Initialize SSPxSTAT register
• Initialize SSPxCON1 register
• Set SSPEN bit to enable the module
FIGURE 19-2:
DS39932D-page 276
output control)
MSSP2, see
Select
level (if master device)
and multiplexed with ANx function)
or input (Slave mode)
multiplexed with ANx function)
and multiplexed with ANx function)
(PPS)”)
ENABLING SPI I/O
SPI Master SSPM<3:0> = 00xxb
Section 10.7 “Peripheral Pin
MSb
PROCESSOR 1
Serial Input Buffer
SPI MASTER/SLAVE CONNECTION
Shift Register
(SSPxBUF)
(SSPxSR)
LSb
SDOx
SCKx
SDIx
Serial Clock
initiates the data transfer by sending the SCKx signal.
Any MSSP1 serial port function that is not desired may
be overridden by programming the corresponding Data
Direction (TRIS) register to the opposite value. If
individual MSSP2 serial port functions will not be used,
they may be left unmapped.
19.3.5
Figure 19-2
microcontrollers. The master controller (Processor 1)
Data is shifted out of both shift registers on their pro-
grammed clock edge and latched on the opposite edge
of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time. Whether
the data is meaningful (or dummy data) depends on the
application software. This leads to three scenarios for
data transmission:
• Master sends valid data–Slave sends dummy
• Master sends valid data–Slave sends valid data
• Master sends dummy data–Slave sends valid
Note:
data
data
SDOx
SCKx
SDIx
When MSSP2 is used in SPI Master
mode, the SCK2 function must be config-
ured as both an output and input in the
PPS module. SCK2 must be initialized as
an output pin (by writing 0x0A to one of
the
SCK2IN must also be mapped to the
same pin, by initializing the RPINR22 reg-
ister. Failure to initialize SCK2/SCK2IN as
both output and input will prevent the
module from receiving data on the SDI2
pin, as the module uses the SCK2IN sig-
nal to latch the received data.
TYPICAL CONNECTION
illustrates a typical connection between two
SPI Slave SSPM<3:0> = 010xb
MSb
Serial Input Buffer
RPORx
Shift Register
PROCESSOR 2
(SSPxBUF)
(SSPxSR)
 2011 Microchip Technology Inc.
registers).
LSb
Additionally,