PIC18F24J11 MICROCHIP [Microchip Technology], PIC18F24J11 Datasheet - Page 93

• Manufacturer Part Number: PIC18F24J11
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

TABLE 6-4:
 2011 Microchip Technology Inc.
DMACON2
HLVDCON
PORTE
PORTD
PORTC
PORTB
PORTA
SPBRGH1
BAUDCON1
SPBRGH2
BAUDCON2
TMR3H
TMR3L
T3CON
TMR4
PR4
T4CON
SSP2BUF
SSP2ADD/
SSP2MSK
SSP2STAT
SSP2CON1
SSP2CON2
CMSTAT
PMADDRH/
PMDOUT1H
PMADDRL/
PMDOUT1L
PMDIN1H
PMDIN1L
TXADDRL
TXADDRH
RXADDRL
RXADDRH
DMABCL
DMABCH
PMCONH
PMCONL
PMMODEH
PMMODEL
Legend:
Note
File Name
1:
2:
3:
4:
5:
6:
(5)
(5)
(5)
(5)
(4)
(5)
(5)
(5)
(5)
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs.
Bit 21 of the PC is only available in Serial Programming (SP) modes.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
Alternate names and definitions for these bits when the MSSP module is operating in I
Masking Modes”
These bits and/or registers are only available in 44-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are shown for
44-pin devices.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have different
functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information.
EUSART1 Baud Rate Generator Register High Byte
EUSART2 Baud Rate Generator Register High Byte
Timer3 Register High Byte
Timer3 Register Low Byte
Timer4 Register
Timer4 Period Register
MSSP2 Receive Buffer/Transmit Register
MSSP2 Address Register (I
Parallel Port Out Data High Byte (Buffer 1)
Parallel Master Port Address Low Byte
Parallel Port Out Data Low Byte (Buffer 0)
Parallel Port In Data High Byte (Buffer 1)
Parallel Port In Data Low Byte (Buffer 0)
SPI DMA Transit Data Pointer Low Byte
SPI DMA Receive Data Pointer Low Byte
SPI DMA Byte Count Low Byte
VDIRMAG
TMR3CS1
DLYCYC3
ABDOVF
ABDOVF
WAITB1
PMPEN
WCOL
GCEN
GCEN
RDPU
MSK7
BUSY
CSF1
Bit 7
SMP
RD7
RC7
RB7
RA7
—
—
—
—
—
—
REGISTER FILE SUMMARY (PIC18F46J11 FAMILY)
T4OUTPS3
TMR3CS0
DLYCYC2
ACKSTAT
ACKSTAT
for details.
WAITB0
SSPOV
BGVST
IRQM1
RCIDL
RCIDL
REPU
MSK6
CSF0
Bit 6
CKE
RD6
RC6
RB6
RA6
CS1
—
—
—
—
—
2
Parallel Master Port Address High Byte
T4OUTPS2 T4OUTPS1
C™ Slave mode), MSSP2 Baud Rate Reload Register (I
ADMSK5
DLYCYC1
T3CKPS1
WAITM3
RXDTP
RXDTP
SSPEN
ACKDT
IRQM0
IRVST
MSK5
Bit 5
RD5
RC5
RB5
RA5
ALP
D/A
—
—
—
—
—
—
(4)
ADMSK4
ADRMUX1
DLYCYC0
T3CKPS0
HLVDEN
WAITM2
ACKEN
TXCKP
TXCKP
INCM1
MSK4
Bit 4
RD4
RC4
CKP
RB4
—
—
—
—
—
—
—
P
(4)
SPI DMA Transit Data Pointer High Byte
SPI DMA Receive Data Pointer High Byte
T4OUTPS0
ADMSK3
ADRMUX0
INTLVL3
WAITM1
HLVDL3
SSPM3
BRG16
BRG16
INCM0
MSK3
RCEN
CS1P
Bit 3
RD3
RC4
RB3
RA3
PIC18F46J11 FAMILY
—
—
—
—
S
(4)
ADMSK2
TMR4ON
MODE16
INTLVL2
T3SYNC
PTBEEN
WAITM0
HLVDL2
SSPM2
MSK2
Bit 2
RE2
RD2
RC2
RB2
RA2
R/W
PEN
BEP
—
—
—
—
(4)
2
C™ Slave mode. See
2
C Master mode)
SPI DMA Receive Data
Pointer High Byte
ADMSK1
T4CKPS1
PTWREN
INTLVL1
HLVDL1
WAITE1
MODE1
SSPM1
COUT2
WRSP
MSK1
RSEN
RD16
WUE
WUE
Bit 1
RE1
RD1
RC1
RB1
RA1
UA
(4)
T4CKPS0
TMR3ON
PTRDEN
INTLVL0
HLVDL0
WAITE0
ABDEN
ABDEN
MODE0
SSPM0
COUT1
RDSP
MSK0
Bit 0
SEN
SEN
RE0
RD0
RC0
RB0
RA0
Section 19.5.3.2 “Address
BF
DS39932D-page 93
xxx- xxxx
0000 0000
0000 0000
00-- -xxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 0000
0100 0-00
0000 0000
0100 0-00
xxxx xxxx
xxxx xxxx
0000 -000
0000 0000
1111 1111
-000 0000
xxxx xxxx
0000 0000
1111 1111
0000 0000
0000 0000
0000 0000
---- --11
-000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
---- 0000
0000 0000
---- 0000
0000 0000
---- --00
0--0 0000
000- 0000
0000 0000
0000 0000
POR, BOR
Value on
Details
72, 285
72, 330
72, 330
73, 215
73, 225
73, 363
73, 179
73, 179
73, 179
73, 179
73, 172
73, 173
73, 174
73, 175
73, 295
73, 295
73, 273
73, 293
73, 294
Page:
on
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