PIC18F24J11 MICROCHIP [Microchip Technology], PIC18F24J11 Datasheet - Page 346

• Manufacturer Part Number: PIC18F24J11
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F46J11 FAMILY
20.3.2
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTAx<5>) or the Continuous Receive
Enable bit, CREN (RCSTAx<4>). Data is sampled on
the RXx pin on the falling edge of the clock.
If enable bit, SREN, is set, only a single word is
received. If enable bit, CREN, is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
To set up a Synchronous Master Reception:
1.
2.
FIGURE 20-13:
DS39932D-page 346
RC6/TX1/CK1/RP17
RC6/TX1/CK1/RP17
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. This example is equally applicable
Initialize the SPBRGHx:SPBRGx registers for
the appropriate baud rate. Set or clear the
BRG16 bit, as required, to achieve the desired
baud rate.
Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
pin (TXCKP = 0)
pin (TXCKP = 1)
SDO1/RP18 pin
RC7/RX1/DT1/
to EUSART2 (RPn1/TX2/CK2 and RPn2/RX2/DT2).
(Interrupt)
RC1IF bit
RCREG1
bit SREN
SREN bit
CREN bit
Write to
EUSART SYNCHRONOUS MASTER
RECEPTION
Read
Q2
‘0’
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
bit 0
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 1
bit 2
bit 3
3.
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the error by clearing
11. If using interrupts, ensure that the GIE and PEIE
Ensure bits, CREN and SREN, are clear.
If interrupts are desired, set enable bit, RCxIE.
If 9-bit reception is desired, set bit, RX9.
If a single reception is required, set bit, SREN.
For continuous reception, set bit, CREN.
Interrupt flag bit, RCxIF, will be set when
reception is complete and an interrupt will be
generated if the enable bit, RCxIE, was set.
Read the RCSTAx register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREGx register.
bit, CREN.
bits in the INTCON register (INTCON<7:6>) are
set.
bit 4
bit 5
 2011 Microchip Technology Inc.
bit 6
bit 7
Q1 Q2 Q3 Q4
‘0’