PIC18F24J11 MICROCHIP [Microchip Technology], PIC18F24J11 Datasheet - Page 92

• Manufacturer Part Number: PIC18F24J11
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F46J11 FAMILY
TABLE 6-4:
DS39932D-page 92
RCREG1
TXREG1
TXSTA1
RCSTA1
SPBRG2
RCREG2
TXREG2
TXSTA2
EECON2
EECON1
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
RCSTA2
OSCTUNE
T1GCON
RTCVALH
RTCVALL
T3GCON
TRISE
TRISD
TRISC
TRISB
TRISA
ALRMCFG
ALRMRPT
ALRMVALH
ALRMVALL
LATE
LATD
LATC
LATB
LATA
DMACON1
DMATXBUF
Legend:
Note
File Name
1:
2:
3:
4:
5:
6:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs.
Bit 21 of the PC is only available in Serial Programming (SP) modes.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
Alternate names and definitions for these bits when the MSSP module is operating in I
Masking Modes”
These bits and/or registers are only available in 44-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are shown for
44-pin devices.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have different
functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information.
EUSART1 Receive Register
EUSART1 Transmit Register
EUSART2 Baud Rate Generator Register Low Byte
EUSART2 Receive Register
EUSART2 Transmit Register
Program Memory Control Register 2 (not a physical register)
RTCC Value Register Window High Byte, Based on RTCPTR<1:0>
RTCC Value Register Window Low Byte, Based on RTCPTR<1:0>
Alarm Value Register Window High Byte, Based on ALRMPTR<1:0>
Alarm Value Register Window Low Byte, Based on ALRMPTR<1:0>
SPI DMA Transmit Buffer
TMR1GE
TMR3GE
ALRMEN
PMPIP
PMPIF
PMPIE
SSCON1
OSCFIP
OSCFIF
OSCFIE
INTSRC
SSP2IP
SSP2IE
TRISD7
TRISC7
TRISB7
TRISA7
SSP2IF
ARPT7
LATD7
LATC7
LATB7
CSRC
CSRC
LATA7
SPEN
SPEN
Bit 7
—
—
—
REGISTER FILE SUMMARY (PIC18F46J11 FAMILY)
(5)
(5)
(5)
SSCON0
for details.
T1GPOL
T3GPOL
BCL2IE
TRISD6
TRISC6
TRISB6
TRISA6
BCL2IP
BCL2IF
PLLEN
CHIME
ARPT6
CM2IP
CM2IF
CM2IE
LATD6
LATC6
LATB6
LATA6
ADIP
ADIF
ADIE
Bit 6
RX9
RX9
TX9
TX9
—
—
—
AMASK3
WPROG
TRISD5
TRISC5
T1GTM
T3GTM
TRISB5
TRISA5
ARPT5
CM1IP
CM1IF
CM1IE
LATD5
LATC5
TXINC
RC2IP
RC2IF
RC2IE
RC1IP
RC1IF
RC1IE
LATB5
LATA5
TXEN
SREN
TXEN
SREN
TUN5
Bit 5
—
—
T1GSPM
T3GSPM
AMASK2
TRISD4
TRISC4
TRISB4
ARPT4
RXINC
LATD4
LATC4
LATB4
SYNC
CREN
SYNC
TX2IP
TX2IE
TX1IP
TX1IE
CREN
FREE
TX2IF
TX1IF
TUN4
Bit 4
—
—
—
—
—
—
—
DUPLEX1
T1DONE
T3DONE
AMASK1
WRERR
T1GGO/
T3GGO/
TMR4IP
TMR4IF
TMR4IE
SENDB
ADDEN
SENDB
BCL1IP
BCL1IE
SSP1IP
SSP1IF
SSP1IE
ADDEN
TRISD3
TRISC3
TRISB3
TRISA3
BCL1IF
ARPT3
LATD3
LATC3
LATB3
LATA3
TUN3
Bit 3
—
—
DUPLEX0
AMASK0
CTMUIP
CTMUIF
CTMUIE
T1GVAL
T3GVAL
CCP1IP
CCP1IF
CCP1IE
TRISD2
TRISC2
TRISE2
TRISB2
TRISA2
ARPT2
WREN
LATD2
LATC2
BRGH
BRGH
LATE2
LATB2
LATA2
FERR
LVDIP
LVDIF
LVDIE
FERR
TUN2
Bit 2
2
C™ Slave mode. See
ALRMPTR1
DLYINTEN
TMR3GIP
TMR3GIF
TMR3GIE
T1GSS1
T3GSS1
TMR3IP
TMR3IF
TMR3IE
TMR2IP
TMR2IF
TMR2IE
TRISD1
TRISC1
TRISE1
TRISB1
TRISA1
ARPT1
LATD1
LATC1
OERR
OERR
LATE1
LATB1
LATA1
TRMT
TRMT
TUN1
Bit 1
WR
 2011 Microchip Technology Inc.
ALRMPTR0
T1GSS0
T3GSS0
RTCCIP
RTCCIE
TMR1IP
TMR1IE
RTCCIF
CCP2IP
CCP2IF
CCP2IE
TMR1IF
TRISE0
TRISD0
TRISC0
TRISB0
TRISA0
DMAEN
ARPT0
LATE0
LATD0
LATC0
LATB0
LATA0
RX9D
RX9D
TX9D
TX9D
TUN0
Bit 0
Section 19.5.3.2 “Address
—
0000 0000
0000 0000
0000 0010
0000 0000
0000 0000
0000 0000
0000 0000
0000 0010
---- ----
--00 x00-
1111 1111
0000 0000
0000 0000
111- 1111
000- 0000
000- 0000
1111 1111
0000 0000
0000 0000
0000 0000
0000 0000
0000 0x00
0xxx xxxx
0xxx xxxx
0000 0x00
---- -111
1111 1111
1111 1111
1111 1111
111- 1111
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
---- -xxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- xxxx
0000 0000
xxxx xxxx
POR, BOR
Value on
71, 328
71, 105
71, 128
71, 122
71, 125
71, 127
71, 121
71, 124
71, 126
71, 120
71, 123
72, 216
72, 231
72, 232
72, 284
Details
71, 328
71, 329
72, 329
72, 202
Page:
72, 42
on
71
71
71
71
71
71
72
72
72
72
72
72
72
72
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