PIC18F24J11 MICROCHIP [Microchip Technology], PIC18F24J11 Datasheet - Page 350

• Manufacturer Part Number: PIC18F24J11
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F46J11 FAMILY
20.4.2
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep, or any
Idle mode and bit, SREN, which is a “don’t care” in
Slave mode.
If receive is enabled by setting the CREN bit prior to
entering Sleep or any Idle mode, then a word may be
received while in this low-power mode. Once the word
is received, the RSR register will transfer the data to the
RCREGx register. If the RCxIE enable bit is set, the
interrupt generated will wake the chip from the
low-power mode. If the global interrupt is enabled, the
program will branch to the interrupt vector.
TABLE 20-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
DS39932D-page 350
INTCON
PIR1
PIE1
IPR1
PIR3
PIE3
IPR3
RCSTAx
RCREGx
TXSTAx
BAUDCONx ABDOVF
SPBRGHx
SPBRGx
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Note 1:
Name
These pins are only available on 44-pin devices.
EUSART SYNCHRONOUS SLAVE
RECEPTION
EUSARTx Receive Register
EUSARTx Baud Rate Generator Register High Byte
EUSARTx Baud Rate Generator Register Low Byte
GIE/GIEH PEIE/GIEL TMR0IE
PMPIE
PMPIP
PMPIF
SSP2IF
SSP2IE
SSP2IP
SPEN
CSRC
Bit 7
(1)
(1)
(1)
BCL2IF
BCL2IE
BCL2IP
RCIDL
ADIE
ADIP
ADIF
Bit 6
RX9
TX9
RXDTP
RC1IE
RC1IP
RC1IF
RC2IF
RC2IE
RC2IP
SREN
TXEN
Bit 5
TXCKP
INT0IE
CREN
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
SYNC
Bit 4
TMR4IF
TMR4IE
TMR4IP
SSP1IE
SSP1IP
ADDEN
SSP1IF
SENDB
BRG16
To set up a Synchronous Slave Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
RBIE
Bit 3
Enable the synchronous master serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
If interrupts are desired, set enable bit, RCxIE.
If 9-bit reception is desired, set bit, RX9.
To enable reception, set enable bit, CREN.
Flag bit, RCxIF, will be set when reception is
complete. An interrupt will be generated if
enable bit, RCxIE, was set.
Read the RCSTAx register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREGx register.
If any error occurred, clear the error by clearing
bit, CREN.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
CTMUIF TMR3GIF
CTMUIE TMR3GIE RTCCIE
CTMUIP TMR3GIP RTCCIP
TMR0IF
CCP1IE
CCP1IP
CCP1IF
BRGH
FERR
Bit 2
—
TMR2IF
TMR2IE
TMR2IP
INT0IF
OERR
TRMT
WUE
 2011 Microchip Technology Inc.
Bit 1
TMR1IF
TMR1IE
TMR1IP
RTCCIF
ABDEN
RX9D
TX9D
RBIF
Bit 0
on Page:
Values
Reset
69
72
72
72
72
72
72
72
72
72
73
73
72