PIC18F24J11 MICROCHIP [Microchip Technology], PIC18F24J11 Datasheet - Page 46

• Manufacturer Part Number: PIC18F24J11
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F46J11 FAMILY
3.5
When the PRI_IDLE mode is selected, the designated
primary
interruption. In secondary clock modes (SEC_RUN
and SEC_IDLE), the Timer1 oscillator is operating and
providing the device clock. The Timer1 oscillator may
also run in all power-managed modes if required to
clock Timer1 or Timer3.
In internal oscillator modes (RC_RUN and RC_IDLE),
the internal oscillator block provides the device clock
source. The 31 kHz INTRC output can be used directly
to provide the clock and may be enabled to support
various
power-managed mode (see
Timer
and
information on WDT, FSCM and Two-Speed Start-up).
The INTOSC output at 8 MHz may be used directly to
clock the device or may be divided down by the
postscaler. The INTOSC output is disabled if the clock
is provided directly from the INTRC output.
If Sleep mode is selected, all clock sources, which are
no longer required, are stopped. Since all the transistor
switching currents have been stopped, Sleep mode
achieves the lowest current consumption of the device
(only leakage currents) outside of Deep Sleep mode.
Enabling any on-chip feature that will operate during
Sleep mode increases the current consumed during
Sleep mode. The INTRC is required to support WDT
operation. The Timer1 oscillator may be operating to
support an RTC. Other features may be operating that
do not require a device clock source (i.e., MSSP slave,
PMP, INTx pins, etc.). Peripherals that may add
significant
Section 29.2 “DC Characteristics: Power-Down and
Supply Current PIC18F46J11 Family
DS39932D-page 46
Section 26.5 “Fail-Safe Clock Monitor”
(WDT)”,
Effects of Power-Managed Modes
on Various Clock Sources
special
oscillator
current
Section 26.4 “Two-Speed Start-up”
features
continues
consumption
Section 26.2 “Watchdog
regardless
to
are
(Industrial)”.
run
listed
for more
of
without
the
in
3.6
Power-up delays are controlled by two timers so that no
external Reset circuitry is required for most applica-
tions. The delays ensure that the device is kept in
Reset until the device power supply is stable under
normal circumstances and the primary clock is operat-
ing and stable. For additional information on power-up
delays, see Section 5.6 “Power-up Timer (PWRT)”.
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (parameter 33,
Table
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (HS mode). The OST does
this by counting 1024 oscillator cycles before allowing
the oscillator to clock the device.
There is a delay of interval, T
Table
becomes ready to execute instructions. This delay runs
concurrently with any other delays. This may be the only
delay that occurs when any of the internal oscillator or
EC modes are used as the primary clock source.
29-15), following POR, while the controller
29-15).
Power-up Delays
 2011 Microchip Technology Inc.
CSD
(parameter 38,