PIC18F24J11 MICROCHIP [Microchip Technology], PIC18F24J11 Datasheet - Page 63

• Manufacturer Part Number: PIC18F24J11
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

5.0
The PIC18F46J11 family of devices differentiates
among various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
i)
j)
This section discusses Resets generated by MCLR,
POR and BOR, and covers the operation of the various
start-up timers.
For information on WDT Resets, see
“Watchdog Timer
see Section 6.1.4.4 “Stack Full and Underflow
Resets” and for Deep Sleep mode, see
“Deep Sleep
FIGURE 5-1:
 2011 Microchip Technology Inc.
V
Note 1: The V
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during power-managed modes
Watchdog
execution)
Configuration Mismatch (CM)
Brown-out Reset (BOR)
RESET Instruction
Stack Full Reset
Stack Underflow Reset
Deep Sleep Reset
MCLR
DDCORE
V
DD
RESET
2: The V
Deep Sleep Reset
Configuration bit. On “F” devices, the V
CONFIG3L<DSBOREN>.
Sleep mode. The V
Mode”.
Pointer
Stack
Configuration Word Mismatch
PWRT
Timer
Brown-out
INTRC
( )_IDLE
V
Time-out
DD
DDCORE
Reset
DD
Detect
WDT
(WDT)”. For Stack Reset events,
Sleep
monitoring BOR circuit can be enabled or disabled on “LF” devices based on the CONFIG3L<DSBOREN>
Rise
External Reset
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Stack Full/Underflow Reset
(1)
RESET Instruction
(WDT)
monitoring BOR circuit is only implemented on “F” devices. It is always used, except while in Deep
POR Pulse
PWRT
DDCORE
LF: 11-bit Ripple Counter
F: 5-bit Ripple Counter
Brown-out
Reset
Reset
monitoring BOR circuit has a trip point threshold of VBOR (parameter D005).
(2)
Section 26.2
Section 4.6
(during
DD
monitoring BOR circuit is only enabled during Deep Sleep mode by
PIC18F46J11 FAMILY
Figure 5-1
on-chip Reset circuit.
5.1
Device Reset events are tracked through the RCON
register
indicate that a specific Reset event has occurred. In
most cases, these bits can only be set by the event and
must be cleared by the application after the event. The
state of these flag bits, taken together, can be read to
indicate the type of Reset that just occurred. This is
described in more detail in
Registers”.
The ECON register also has a control bit for setting
interrupt priority (IPEN). Interrupt priority is discussed
in Section 9.0 “Interrupts”.
(Register
RCON Register
provides a simplified block diagram of the
5-1). The lower five bits of the register
Section 5.7 “Reset State of
S
R
Q
DS39932D-page 63
Chip_Reset